Nanosheet devices include a vertical stack of channel layers interconnecting a source and a drain. Advantageously, the channel layers are suspended between the source and the drain, thus enabling a gate-all-around (or GAA) design.
A compressively-strained channel for p-channel field-effect transistors (p-FETs) serves to increase the hole mobility and thus enhance device performance. With current nanosheet device designs however, the source and the drains formed at the ends of the channels often have a high defect density, and thus have a limited effect on inducing compressive strain in the channels.
Therefore, nanosheet device fabrication techniques that effectively induce compressive strain in the channel layers, and hence improve overall device performance, would be desirable.